The present subject matter relates to a semiconductor memory device, and more particularly, to a technology for reducing an overall size of a semiconductor memory device by reducing an area of an inversion bus.
A write data bus inversion (WDBI) function is used to reduce simultaneous switching output (SSO) noise by minimizing data variation when data is inputted to a memory device. Meanwhile, a read data bus inversion (RDBI) function is used to reduce the SSO noise by minimizing data variation when data is outputted from a memory device.
The memory device determines whether data is inverted data or not by receiving inversion information such as WDBI together with data from a memory controller to a memory device when data is inputted, and the memory device also determines whether data is inverted data or not by receiving inversion information such as RDBI together with data from the memory device to the memory controller when data is outputted.
FIG. 1 is a diagram illustrating a semiconductor memory device having a four-bank quarter structure according to the related art.
Referring to FIG. 1, each of four banks is divided into four sectors. In FIG. 1, ‘X’ denotes circuits for row operations, and ‘Y’ denotes circuits for column operations.
Also, ‘CPERI’ denotes a region having circuits related to a clock. ‘DPERI’ denotes a region having circuits related to data input and data output.
FIG. 2 is a diagram illustrating exchanging data and inversion information between data input circuits and banks. FIG. 2 shows only one quarter.
As shown in FIG. 2, DQ blocks 210 to 280 are blocks having a data input circuit and a data output circuit, which are disposed in each of data pins. A DBI block 290 denotes a block having an inversion input circuit and an inversion output circuit, which are disposed in a DBI pin.
At first, data flow in a memory device for a read/write operation will be described.
In a write operation, data is consecutively inputted to data pins of a memory device in serial. The data pins include data input circuits 210 and 280, respectively. Actually, the data input circuits are included in the DQ blocks 210 and 280. For convenience, reference numerals 210 to 280 are assigned to the data input circuits, hereinafter. The data input circuits 210 to 280 sort serially inputted data to parallel data and transfer the parallel data to global lines GIO0<0:7> to GIO7<0:7>. If the memory device employs a 8-bit prefetch scheme, the data input circuits 210 to 280 sort serially inputted 8 data to parallel data and transfer the parallel data to the global lines GIO0<0:7> to GIO7<0:7>. That is, data inputted to one DQ pin, for example, DQ0, is converted to parallel data, and the parallel data is loaded on a global line, for example, GIO0<0:7>. Such global lines GIO0<0:7> to GIO7<0:7> are connected to Y blocks 11, 21, 31, and 41 of all banks, and data are written in parallel at one of banks 10 to 40 selected by a bank address.
In a read operation, data are outputted from one of the banks 10 to 40 selected by a bank address in parallel. The data pins include data output circuits 210 to 280, respectively. Actually, the data output circuits are included in the DQ blocks 210 and 280. For convenience, reference numerals 210 to 280 are assigned to the data output circuits, hereinafter. The data output circuits 210 to 280 sort data that are transferred in parallel through global lines GIO0<0:7> to GIO7<0:7> and output the sorted data to the outside of a chip through the data pins. For example, if the memory device employs a 8-bit prefetch scheme, data transferred through 8 global lines such as GIO0<0:7> to a data output circuit such as 210 are sorted into serial data, and the serial data is outputted through data pins.
Although the global lines GIO0<0:7> to GIO7<0:7> transfer data of a read path and data of a write path in the memory device of FIG. 2, two separate global lines may be included in a memory device for transferring data of a read path and data of a write path according to design. For example, GIO may be divided into RGIO and WGIO.
Flow of inversion information DBI for a read/write operation of a memory device will be described.
In a write operation, write inversion information WDBI is consecutively inputted to an inversion pin in serial. The write inversion information WDBI denotes whether data inputted from the outside of a memory is inverted data or not in a write operation. An inversion input circuit 290 sorts serially inputted write inversion information WDBI to parallel data and transfers the parallel data to the write inversion bus WDBI<0:7>. Actually, the inversion input circuit is included in the DBI block 290. For convenience, a reference numeral 290 is also assigned to the inversion input circuit, hereinafter. The WDBI uses the same prefetch scheme. Therefore, if the memory device employs a 8-bit prefetch scheme, the inversion input circuit 290 sorts serially inputted 8 write inversion information WDBI in parallel data and transfers the parallel data to a write inversion bus WDBI<0:7>. The write inversion bus WDBI<0:7> includes 8 lines.
The write inversion bus WDBI<0:7> transfers the write inversion information to Y blocks 11, 21, 31 and 41, of each bank. The Y blocks 11, 21, 31, and 41 of each bank include write drivers WTDRV for transferring data of global lines GIO0<0:7> to GIO7<0:7> to local lines LIO/LIOB of banks 10, 20, 30, and 40. The write drivers invert and non-invert data of the global lines GIO0<0:7>˜GIO7<0:7> according to the write inversion information WDBI<0:7> and transfers the data to the local lines. Since each of the banks 10 to 40 includes local lines LIO/LIOB as many as the number of the global lines GIO0<0:7> to GIO7<0:7>, each of the banks 10 to 40 includes write drivers corresponding to the number of global lines GIO0<0:7> to GIO7<0:7>. For example, a Y block 11 includes 64 write drivers.
In a read operation, an inversion generator 300 in a memory device generates the read inversion information RDBI<0:7>. Since a memory device outputs stored data in the read operation, the memory device must generate read inversion information RDBI<0:7>, inverts or non-inverts data according to the generated read inversion information RDBI<0:7>, and outputs the data. The inversion generator 300 generates read inversion information RDBI<0> as ‘1’ when more than five data among eight data GIO0<0> to GIO7<0> are ‘0’ in a DC mode. The inversion generator 300 generates read inversion information RDBI<0> as ‘1’ if more than 5 data among data GIO0<0> to GIO7<0> transit, compared with previous data in an AC mode. Since a related specification defines how the inversion generator 300 generate read inversion information RDBI<0:7>, detail description thereof is omitted.
The read inversion information generated by the inversion generator 300 is transferred to the read inversion bus RDBI<0:7>, and finally transferred to each of the data output circuits 210 to 280. The data output circuits 210 to 280 invert or non-invert data according to the read inversion information RDBI<0:7>.
The read inversion bus RDBI<0:7> transfers read inversion information to the inversion output unit 290. It is because the memory device must output read inversion information to the outside of a memory device in the read operation.
Since the drawings illustrate one quarter of the memory device having a quarter bank structure, the Y blocks 11, 21, 31, and 41 of each bank are connected to global lines GIO0<0:7>˜GIO7<0:7> corresponding to 8 data pins. Remaining banks (not shown) are also connected to global lines corresponding to 8 data pins. For example, banks 50, 60, 70, and 80 are connected to global lines corresponding to 8th to 15th data pins. Since one inversion pin manages inversion information of data inputted/outputted through 8 data pins, each of remaining quarters includes one inversion pin.
FIG. 3 is a diagram illustrating exchanging data and inversion information between data input circuits 210 to 280 and banks 10 to 40 like FIG. 2. However, parts of the Y blocks 11, 21, 31, and 41 of the bank are disposed around data pins and inversion pins. Like reference numerals denote like element in FIGS. 2 and 3.
Global lines GIO0<0:7> to GIO7<0:7> must be connected from DQ blocks 210 to 280 to each of banks 10 to 40. Write inversion buses WDBI<0:7> are also connected from the DBI block 290 to each of the blocks 10 to 40. Therefore, when the Y blocks 11, 21, 31, and 41 of the banks are disposed like FIG. 2, the lengths of the global lines GIO0<0:7> to GIO7<0:7> and the write inversion buses WDBI<0:7> become excessively longer, thereby occupying a large area in a chip. Therefore, parts of the Y blocks 11, 21, 31, and 41 such as data input/output units 12, 22, 32, and 42 are disposed around data pins and inversion pins in the memory devices as shown in FIG. 3.
The input/output units 12, 22, 32, and 42 are parts for inputting and outputting data in the Y blocks 11, 21, 31, and 41. The input/output units 12, 22, 32, and 42 include a writer driver WTDRV and a sense amp IOSA for exchanging data with the global lines GIO0<0:7> to GIO7<0:7>.
By disposing the input/output units 12, 22,32, and 42 like FIG. 3, the lengths of the global lines GIO0<0:7> to GIO7<0:7> and the write inversion bus WDBI<0:7> can be shortened. As a result, the overall area of memory device can be reduced too.
FIG. 4 is a diagram illustrating a data input circuit and a data output circuit in a DQ block 210 of FIG. 2.
The data input circuit 410 includes a data buffer 411, a serial-to-parallel converter 412, and a driver 413.
The data buffer 41 buffers data inputted to a data pad DQ PAD that is a pad on a wafer connected to a data pin and transfers the buffered data to the serial-to-parallel converter 412. Data is consecutively inputted to the data pad according to a prefetch scheme. In case of using an 8 bit prefetch scheme, 8 data are consecutively inputted in serial corresponding to one write command.
The serial to parallel converter 412 sorts inputted serial data to parallel data. How serial data is sorted to parallel data is decided according to a type of a prefetch scheme. For example, in case of using a 8-bit prefetch scheme, 8 serial input data are outputted through 8 lines GIO_PRE0<0:7> in parallel.
The driver 413 loads the parallel data GIO_PRE0<0:7> on the global lines GIO0<0:7>. For example, the driver 413 is strobed by a clock TDQSS_CLK and loads data on the global lines GIO0<0:7>. The TDQSS_CLK is a clock having a cycle as much as a gap between consecutive write commands.
The data output circuit 420 includes an output driver 421, a parallel to serial converter 422, and a read inversion unit 423.
The read inversion unit 423 inverts or non-inverts data GIO0<0:7> to output according to read inversion information RDBI<0:7>. If the read inversion information RDBI<0:7> is ‘1,’ the read inversion unit 423 inverts the data to output. If the read inversion information RDBI<0:7> is ‘0,’ the read inversion unit 433 does not invert the data. The read inversion unit 423, as shown, includes XOR gates for receiving data of the global lines GIO0<0:7> and the read inversion information RDBI<0:7>.
The parallel to serial converter 422 converts parallel data outputted from the read inversion unit 423 to serial data. In case of using a 8-bit prefetch scheme, the parallel to serial converter 422 converts data of 8 lines to serial data. That is, the parallel to serial converter 422 may perform the opposite function of the serial to parallel converter 412.
The output driver 421 outputs the serial data from the parallel to serial converter 422 to the outside of the memory device. That is, the output driver 421 may perform the opposite function of the data input buffer 411.
FIG. 5 is a diagram illustrating an inversion input circuit and an inversion output circuit in a DBI block 290 of FIG. 2.
The inversion input circuit 510 includes an inversion buffer 511, a serial-to-parallel converter 512, and a driver 513.
The inversion buffer 511 buffers write inversion information WDBI_IN inputted to an inversion pad WBI PAD and transfers the buffered write inversion information to the serial-to-parallel converter 512. The write inversion information WDBI_IN is consecutively inputted in serial similar to the data.
The serial-to-parallel converter 512 sorts the serial write inversion information WDBI_IN to parallel data. Except sorting the write inversion information WDBI instead of the data, the serial-to-parallel converter 512 performs the same function of the serial-to-parallel converter 412 of the data input circuit 410.
The driver 513 loads the parallel inversion information WDBI_PRE<0:7> on the write inversion bus WDBI<0:7>. Also, the driver 513 is strobed by a clock TDQSS_CLK and loads the write inversion information WDBI_PRE<0:7> on the write inversion bus WDBI<0:7>.
The inversion output circuit 520 includes a parallel to serial converter 522 and an output driver 521.
The parallel to serial converter 522 converts the read inversion information transferred to the read inversion bus RDBI<0:7> to serial data and outputs the serial data. The output driver 521 outputs the serial read inversion information RDBI_OUT to the outside of the memory device.
FIG. 6 is a diagram illustrating write drivers and write inversion units in an input/output unit 12 of FIG. 3 and an Y block 11 of FIG. 2.
A write inversion unit 610 is disposed in front of write drivers 621 to 628. The write inversion unit 610 inverts or non-inverts data GIO0<0:7> stored in a memory device according to the write inversion information that is transferred through the write inversion bus WDBI<0:7>. If the write inversion information WDBI<0:7> is ‘1,’ the write inversion unit 610 inverts the data. If the write inversion information WDBI<0:7> is ‘0,’ the write inversion unit 610 non-inverts the data. The write inversion unit 610 includes XOR gates like the read inversion unit 433.
The write drivers 621 to 628 transfer data with write inversion information RDBI<0:7> reflected by the write inversion unit 610 to the local lines LIO/LIOB0<0:7> in the bank. The write enable signal WTEN inputted to the write drivers 621 to 628 is enabled in a write operation. The write enable signal WTEN controls the writer drivers 621 to 628 not to operate in a read operation.
FIG. 6 illustrates the write drivers 621 to 628 only, which transfers the data GIO0<0:7> inputted to one data pin DQ0 to the local lines LIO/LIOB0<0:7>. When a memory device includes a quarter bank structure, one of blocks 11, 21, 31, and 41 or the input/output units 12, 22, 32, and 42 includes 64 write drivers, and the write inversion unit 610 includes 64 XOR gates.
A semiconductor memory device according to the related art separately includes write inversion buses WDBI<0:7> for transferring write inversion information and read inversion bus RDBI<0:7> for transferring read inversion information in the memory device. If the write inversion bus WDBI<0:7> and the read inversion bus RDBI<0:7> are separately disposed as described above, the memory device needs more lines to realize an inversion function (DBI function). It is a major factor to increase the size of the memory device.
Therefore, it has been required to reduce the number of lines necessary for embodying the DBI function.